The present invention relates generally to integrated circuit devices, and more specifically to a method and layout structure for automatic on-chip clock tuning of an integrated circuit device.
There are many instances in which it is desirable to generate a system clock signal on an integrated circuit device. For instance, given an original frequency provided to the integrated circuit device it may be desirable to generate a system clock signal that is double or quadruple the original frequency. The problem arises in tuning the generated system clock signal to a desired duty cycle. The tuning of the duty cycle is typically achieved in a separate tuning exercise subsequent to the generation of the system clock signal. Such tuning of the duty cycle is time-consuming and must normally be repeated each time the frequency of the system clock signal is changed or generated. It would be advantageous in the art to be able to tune the duty cycle of a system clock signal in such a manner that minimizes time and effort. It would further be advantageous in the art to automatically tune a generated system clock signal to a desired duty cycle.